The present invention relates to a data transfer device and a parallel computer system and more particularly, to a data transfer technique which can be effectively applied to data transfer between a memory and an I/O device in a computer system including workstations or servers or to interconnection between a plurality of such computer systems.
For example, a computer system including workstations or servers employs mainly reduced instruction set computer (RISC) processors. With improvement of such logical system as pipeline control and an operational frequency increased by advancement of semiconductor techniques, the single RISC processor has been increasingly improved.
Requirements demanded for such a system are first to increase the number of transactions processable per unit time especially for each server, and second not only to improve the performance of each CPU but also to provide a mechanism for allowing each CPU to be able to perform parallel processing operation in a plurality of computer systems and to increase the number of external memories such as disk units connectable thereto and the memory capacity thereof.
However, the numbers of CPUs, memories and I/O devices connectable to an identical bus or crossbar switch has its limit by electrical restrictions to load capacitances by which the data transfer operational speed of the bus or crossbar switch is guaranteed or by physical restrictions of manufacturing techniques for the size of a backboard forming the bus or crossbar switch.
For this reason, the hardware of a high-performance server requiring a multiplicity of I/O devices to be connected thereto has, in many cases, such a configuration that a system bus or crossbar switch for connecting a CPU and a memory is connected to I/O buses for connection of I/O devices in a hierarchically-connected relation, i.e., in a multi-layer bus connection relation. For the purpose of enhancing parallel processing capability, a plurality of computer systems each having CPUs are interconnected with each other via the I/O devices.
In order to secure a constant reliability in an overall system even when the number of I/O devices to be connected is increased, it is required that occurrence of a fault in one of the I/O devices cause the influence of the fault not to be transmitted to other CPUs, that is, to be localized.
Further, to nest buses means to make long a logical and physical distance between CPUs or memories and I/O devices. For this reason, when control of the I/O device is carried out directly from the CPU based on CPU instruction operation, there occurs such a problem that its instruction execution time becomes long and the performance of the CPU is degraded by the control of the I/O device. This also causes a data transfer latency between the memory and I/O device to become large. Thus, when data transfer is started directly from the I/O device, prefetch data from the memory or write data to the memory are required to be temporarily saved, which disadvantageously results in that the I/O device must have a large capacity of buffer, thus increasing costs for the I/O device.
Meanwhile, various sorts of devices have been developed in these years. However, sequential development of I/O devices compatible with their own computer systems is costly. Therefore, this requires the I/O devices manufactured by a third party to be built in own computer systems. Further, I/O devices manufactured by third party are generally compatible with industrial standard-based buses such as protocol control information (PCI) buses, and it is important to connect such an industrial standard-based bus as a PCI bus in own computer system, while minimizing the influence of the own computer system on its operating system.
Furthermore, communication of the own computer system with another computer system via the I/O device in order to allow the respective CPUs within the plurality of computer systems to perform parallel operation causes generation of an overhead with low efficiency, because of intervention of the control protocol of the I/O device during the communication between the computer systems. In addition, an upper limit of the data transfer rate is limited to the transfer rate of the I/O device per se.